# New self-checking Booth multipliers

Marc Hunger; Daniel Marienfeld

International Journal of Applied Mathematics and Computer Science (2008)

- Volume: 18, Issue: 3, page 319-328
- ISSN: 1641-876X

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topMarc Hunger, and Daniel Marienfeld. "New self-checking Booth multipliers." International Journal of Applied Mathematics and Computer Science 18.3 (2008): 319-328. <http://eudml.org/doc/207888>.

@article{MarcHunger2008,

abstract = {This work presents the first self-checking Booth-3 multiplier and a new self-checking Booth-2 multiplier using parity prediction. We propose a method which combines error-detection of Booth-3 (or Booth-2) decoder cells and parity prediction. Additionally, code disjointness is ensured by reusing logic for partial product generation. Parity prediction is applied to a carry-save-adder with the standard sign-bit extension. In this adder almost all cells have odd fanouts and faults are detected by the parity. Only one adder cell has an even fanout in the case of Booth-3 multiplication. Especially, for even-number Booth-2 multipliers parity prediction becomes efficient. Since that prediction slightly differs from previous work which describes CSA-folded adders, formulas to predict the parity are developed here. The proposed multipliers are compared experimentally with existing solutions. Only 102% of the area of Booth-2 without error detection is needed for the self-checking Booth-3 multiplier.},

author = {Marc Hunger, Daniel Marienfeld},

journal = {International Journal of Applied Mathematics and Computer Science},

keywords = {booth multiplier; self-checking; parity-prediction; carry-dependent adder; 1-out-of-5 code; Booth multiplier; self-checking, parity-prediction},

language = {eng},

number = {3},

pages = {319-328},

title = {New self-checking Booth multipliers},

url = {http://eudml.org/doc/207888},

volume = {18},

year = {2008},

}

TY - JOUR

AU - Marc Hunger

AU - Daniel Marienfeld

TI - New self-checking Booth multipliers

JO - International Journal of Applied Mathematics and Computer Science

PY - 2008

VL - 18

IS - 3

SP - 319

EP - 328

AB - This work presents the first self-checking Booth-3 multiplier and a new self-checking Booth-2 multiplier using parity prediction. We propose a method which combines error-detection of Booth-3 (or Booth-2) decoder cells and parity prediction. Additionally, code disjointness is ensured by reusing logic for partial product generation. Parity prediction is applied to a carry-save-adder with the standard sign-bit extension. In this adder almost all cells have odd fanouts and faults are detected by the parity. Only one adder cell has an even fanout in the case of Booth-3 multiplication. Especially, for even-number Booth-2 multipliers parity prediction becomes efficient. Since that prediction slightly differs from previous work which describes CSA-folded adders, formulas to predict the parity are developed here. The proposed multipliers are compared experimentally with existing solutions. Only 102% of the area of Booth-2 without error detection is needed for the self-checking Booth-3 multiplier.

LA - eng

KW - booth multiplier; self-checking; parity-prediction; carry-dependent adder; 1-out-of-5 code; Booth multiplier; self-checking, parity-prediction

UR - http://eudml.org/doc/207888

ER -

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