New self-checking Booth multipliers

Marc Hunger; Daniel Marienfeld

International Journal of Applied Mathematics and Computer Science (2008)

  • Volume: 18, Issue: 3, page 319-328
  • ISSN: 1641-876X

Abstract

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This work presents the first self-checking Booth-3 multiplier and a new self-checking Booth-2 multiplier using parity prediction. We propose a method which combines error-detection of Booth-3 (or Booth-2) decoder cells and parity prediction. Additionally, code disjointness is ensured by reusing logic for partial product generation. Parity prediction is applied to a carry-save-adder with the standard sign-bit extension. In this adder almost all cells have odd fanouts and faults are detected by the parity. Only one adder cell has an even fanout in the case of Booth-3 multiplication. Especially, for even-number Booth-2 multipliers parity prediction becomes efficient. Since that prediction slightly differs from previous work which describes CSA-folded adders, formulas to predict the parity are developed here. The proposed multipliers are compared experimentally with existing solutions. Only 102% of the area of Booth-2 without error detection is needed for the self-checking Booth-3 multiplier.

How to cite

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Marc Hunger, and Daniel Marienfeld. "New self-checking Booth multipliers." International Journal of Applied Mathematics and Computer Science 18.3 (2008): 319-328. <http://eudml.org/doc/207888>.

@article{MarcHunger2008,
abstract = {This work presents the first self-checking Booth-3 multiplier and a new self-checking Booth-2 multiplier using parity prediction. We propose a method which combines error-detection of Booth-3 (or Booth-2) decoder cells and parity prediction. Additionally, code disjointness is ensured by reusing logic for partial product generation. Parity prediction is applied to a carry-save-adder with the standard sign-bit extension. In this adder almost all cells have odd fanouts and faults are detected by the parity. Only one adder cell has an even fanout in the case of Booth-3 multiplication. Especially, for even-number Booth-2 multipliers parity prediction becomes efficient. Since that prediction slightly differs from previous work which describes CSA-folded adders, formulas to predict the parity are developed here. The proposed multipliers are compared experimentally with existing solutions. Only 102% of the area of Booth-2 without error detection is needed for the self-checking Booth-3 multiplier.},
author = {Marc Hunger, Daniel Marienfeld},
journal = {International Journal of Applied Mathematics and Computer Science},
keywords = {booth multiplier; self-checking; parity-prediction; carry-dependent adder; 1-out-of-5 code; Booth multiplier; self-checking, parity-prediction},
language = {eng},
number = {3},
pages = {319-328},
title = {New self-checking Booth multipliers},
url = {http://eudml.org/doc/207888},
volume = {18},
year = {2008},
}

TY - JOUR
AU - Marc Hunger
AU - Daniel Marienfeld
TI - New self-checking Booth multipliers
JO - International Journal of Applied Mathematics and Computer Science
PY - 2008
VL - 18
IS - 3
SP - 319
EP - 328
AB - This work presents the first self-checking Booth-3 multiplier and a new self-checking Booth-2 multiplier using parity prediction. We propose a method which combines error-detection of Booth-3 (or Booth-2) decoder cells and parity prediction. Additionally, code disjointness is ensured by reusing logic for partial product generation. Parity prediction is applied to a carry-save-adder with the standard sign-bit extension. In this adder almost all cells have odd fanouts and faults are detected by the parity. Only one adder cell has an even fanout in the case of Booth-3 multiplication. Especially, for even-number Booth-2 multipliers parity prediction becomes efficient. Since that prediction slightly differs from previous work which describes CSA-folded adders, formulas to predict the parity are developed here. The proposed multipliers are compared experimentally with existing solutions. Only 102% of the area of Booth-2 without error detection is needed for the self-checking Booth-3 multiplier.
LA - eng
KW - booth multiplier; self-checking; parity-prediction; carry-dependent adder; 1-out-of-5 code; Booth multiplier; self-checking, parity-prediction
UR - http://eudml.org/doc/207888
ER -

References

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  13. Ocheretnij V., Sogomonya E. S. and Goessel M. (2001). A new code-disjoint sum-bit duplicated carry look-ahead adder for parity codes, Proceedings of the 10th Asian Test Symposium (ATS '01), IEEE Computer Society, Los Alamitos, CA, USA, pp. 365. 
  14. Parhami B. (2001). Instructor's manual for 'Computer Arithmetic: Algorithms and Hardware Designs', Vol. 2: Presentation Material, Oxford University Press, Oxford. 
  15. Shivakumar P., Keckler S. W., Kistler M., Burger D. and Alvisi L. (2002). Modeling the effect of technology trends on the soft error rate of combinatorial logic, Proceedings of the International Conference on Dependable Systems and Networks, pp. 389-398. 
  16. Sparmann U. and Reddy S. M. (1994). On the effectiveness of residue code checking for parallel two's complement multipliers, Proceedings of the 24th International Symposium on Fault Tolerant Computing FTCS-24, IEEE Computer Society Press, Austin, TX, USA, pp. 219-229. 
  17. Sulistyo J. B. and Ha D. S. (2002). A new characterization method for delay and power dissipation of standard cells, VLSI Design 15(3): 667-678. 

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