Test pattern generator for NMOS integrated circuits.
Carles Ferrer Ramis; Jean Pierre Deschamps; Joan Oliver Malagelada; Jordi Carrabina Bordoll; Elena Valderrama Vallés
Qüestiió (1987)
- Volume: 11, Issue: 2, page 81-91
- ISSN: 0210-8054
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topFerrer Ramis, Carles, et al. "Generador de seqüències de test per circuits integrats NMOS. ." Qüestiió 11.2 (1987): 81-91. <http://eudml.org/doc/40079>.
@article{FerrerRamis1987,
author = {Ferrer Ramis, Carles, Deschamps, Jean Pierre, Oliver Malagelada, Joan, Carrabina Bordoll, Jordi, Valderrama Vallés, Elena},
journal = {Qüestiió},
keywords = {Circuitos MOS; Algoritmos; Control de calidad; Fallos; Fabricación; ATPG; D-algorithm; fault detection; switch-level; non-oriented graphs},
language = {cat},
number = {2},
pages = {81-91},
title = {Generador de seqüències de test per circuits integrats NMOS. },
url = {http://eudml.org/doc/40079},
volume = {11},
year = {1987},
}
TY - JOUR
AU - Ferrer Ramis, Carles
AU - Deschamps, Jean Pierre
AU - Oliver Malagelada, Joan
AU - Carrabina Bordoll, Jordi
AU - Valderrama Vallés, Elena
TI - Generador de seqüències de test per circuits integrats NMOS.
JO - Qüestiió
PY - 1987
VL - 11
IS - 2
SP - 81
EP - 91
LA - cat
KW - Circuitos MOS; Algoritmos; Control de calidad; Fallos; Fabricación; ATPG; D-algorithm; fault detection; switch-level; non-oriented graphs
UR - http://eudml.org/doc/40079
ER -
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