Pipelined architectures for the Frequency Domain linear equalizer

George Glentis; Kristina Georgoulakis

International Journal of Applied Mathematics and Computer Science (2006)

  • Volume: 16, Issue: 4, page 525-535
  • ISSN: 1641-876X

Abstract

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In this paper, novel pipelined architectures for the implementation of the frequency domain linear equalizer are presented. The Frequency Domain (FD) LMS algorithm is utilized for the adaptation of equalizer coefficients. The pipelining of the FD LMS linear equalizer is achieved by introducing an amount of time delay into the original adaptive scheme, and following proper delay retiming. Simulation results are presented that illustrate the performance of the effect of the time delay introduced into the adaptation algorithm. The proposed architectures for efficient pipelining of the FD LMS linear equalization algorithm are suitable for implementation on special purpose hardware by means of the ASIC, ASIP or FPGA VLSI processors.

How to cite

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Glentis, George, and Georgoulakis, Kristina. "Pipelined architectures for the Frequency Domain linear equalizer." International Journal of Applied Mathematics and Computer Science 16.4 (2006): 525-535. <http://eudml.org/doc/207811>.

@article{Glentis2006,
abstract = {In this paper, novel pipelined architectures for the implementation of the frequency domain linear equalizer are presented. The Frequency Domain (FD) LMS algorithm is utilized for the adaptation of equalizer coefficients. The pipelining of the FD LMS linear equalizer is achieved by introducing an amount of time delay into the original adaptive scheme, and following proper delay retiming. Simulation results are presented that illustrate the performance of the effect of the time delay introduced into the adaptation algorithm. The proposed architectures for efficient pipelining of the FD LMS linear equalization algorithm are suitable for implementation on special purpose hardware by means of the ASIC, ASIP or FPGA VLSI processors.},
author = {Glentis, George, Georgoulakis, Kristina},
journal = {International Journal of Applied Mathematics and Computer Science},
keywords = {pipelined implementation; frequency domain LMS; adaptive equalization},
language = {eng},
number = {4},
pages = {525-535},
title = {Pipelined architectures for the Frequency Domain linear equalizer},
url = {http://eudml.org/doc/207811},
volume = {16},
year = {2006},
}

TY - JOUR
AU - Glentis, George
AU - Georgoulakis, Kristina
TI - Pipelined architectures for the Frequency Domain linear equalizer
JO - International Journal of Applied Mathematics and Computer Science
PY - 2006
VL - 16
IS - 4
SP - 525
EP - 535
AB - In this paper, novel pipelined architectures for the implementation of the frequency domain linear equalizer are presented. The Frequency Domain (FD) LMS algorithm is utilized for the adaptation of equalizer coefficients. The pipelining of the FD LMS linear equalizer is achieved by introducing an amount of time delay into the original adaptive scheme, and following proper delay retiming. Simulation results are presented that illustrate the performance of the effect of the time delay introduced into the adaptation algorithm. The proposed architectures for efficient pipelining of the FD LMS linear equalization algorithm are suitable for implementation on special purpose hardware by means of the ASIC, ASIP or FPGA VLSI processors.
LA - eng
KW - pipelined implementation; frequency domain LMS; adaptive equalization
UR - http://eudml.org/doc/207811
ER -

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