# Stability of the 4-2 Binary Addition Circuit Cells. Part I

Formalized Mathematics (2008)

- Volume: 16, Issue: 4, page 377-387
- ISSN: 1426-2630

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topKatsumi Wasaki. "Stability of the 4-2 Binary Addition Circuit Cells. Part I." Formalized Mathematics 16.4 (2008): 377-387. <http://eudml.org/doc/266881>.

@article{KatsumiWasaki2008,

abstract = {To evaluate our formal verification method on a real-size calculation circuit, in this article, we continue to formalize the concept of the 4-2 Binary Addition Cell primitives (FTAs) to define the structures of calculation units for a very fast multiplication algorithm for VLSI implementation [11]. We define the circuit structure of four-types FTAs, TYPE-0 to TYPE-3, using the series constructions of the Generalized Full Adder Circuits (GFAs) that generalized adder to have for each positive and negative weights to inputs and outputs [15]. We then successfully prove its circuit stability of the calculation outputs after four-steps. The motivation for this research is to establish a technique based on formalized mathematics and its applications for calculation circuits with high reliability.MML identifier: FTACELL1, version: 7.9.03 4.108.1028},

author = {Katsumi Wasaki},

journal = {Formalized Mathematics},

language = {eng},

number = {4},

pages = {377-387},

title = {Stability of the 4-2 Binary Addition Circuit Cells. Part I},

url = {http://eudml.org/doc/266881},

volume = {16},

year = {2008},

}

TY - JOUR

AU - Katsumi Wasaki

TI - Stability of the 4-2 Binary Addition Circuit Cells. Part I

JO - Formalized Mathematics

PY - 2008

VL - 16

IS - 4

SP - 377

EP - 387

AB - To evaluate our formal verification method on a real-size calculation circuit, in this article, we continue to formalize the concept of the 4-2 Binary Addition Cell primitives (FTAs) to define the structures of calculation units for a very fast multiplication algorithm for VLSI implementation [11]. We define the circuit structure of four-types FTAs, TYPE-0 to TYPE-3, using the series constructions of the Generalized Full Adder Circuits (GFAs) that generalized adder to have for each positive and negative weights to inputs and outputs [15]. We then successfully prove its circuit stability of the calculation outputs after four-steps. The motivation for this research is to establish a technique based on formalized mathematics and its applications for calculation circuits with high reliability.MML identifier: FTACELL1, version: 7.9.03 4.108.1028

LA - eng

UR - http://eudml.org/doc/266881

ER -

## References

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