Area-oriented technology mapping for LUT-based logic blocks

Marcin Kubica; Dariusz Kania

International Journal of Applied Mathematics and Computer Science (2017)

  • Volume: 27, Issue: 1, page 207-222
  • ISSN: 1641-876X

Abstract

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One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique. This paper focuses on using configurable properties of CLBs in the process of logic decomposition and technology mapping. A novel theory and a set of efficient techniques for logic decomposition based on a BDD are proposed. The paper shows that logic optimization can be efficiently carried out by using multiple decomposition. The essence of the proposed synthesis method is multiple cutting of a BDD. A new diagram form called an SMTBDD is proposed. Moreover, techniques that allow finding the best technology mapping oriented to configurability of CLBs are presented. In the experimental section, the presented method (MultiDec) is compared with academic and commercial tools. The experimental results show that the proposed technology mapping strategy leads to good results in terms of the number of CLBs.

How to cite

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Marcin Kubica, and Dariusz Kania. "Area-oriented technology mapping for LUT-based logic blocks." International Journal of Applied Mathematics and Computer Science 27.1 (2017): 207-222. <http://eudml.org/doc/288101>.

@article{MarcinKubica2017,
abstract = {One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique. This paper focuses on using configurable properties of CLBs in the process of logic decomposition and technology mapping. A novel theory and a set of efficient techniques for logic decomposition based on a BDD are proposed. The paper shows that logic optimization can be efficiently carried out by using multiple decomposition. The essence of the proposed synthesis method is multiple cutting of a BDD. A new diagram form called an SMTBDD is proposed. Moreover, techniques that allow finding the best technology mapping oriented to configurability of CLBs are presented. In the experimental section, the presented method (MultiDec) is compared with academic and commercial tools. The experimental results show that the proposed technology mapping strategy leads to good results in terms of the number of CLBs.},
author = {Marcin Kubica, Dariusz Kania},
journal = {International Journal of Applied Mathematics and Computer Science},
keywords = {SMTBDD; FPGA; synthesis; decomposition},
language = {eng},
number = {1},
pages = {207-222},
title = {Area-oriented technology mapping for LUT-based logic blocks},
url = {http://eudml.org/doc/288101},
volume = {27},
year = {2017},
}

TY - JOUR
AU - Marcin Kubica
AU - Dariusz Kania
TI - Area-oriented technology mapping for LUT-based logic blocks
JO - International Journal of Applied Mathematics and Computer Science
PY - 2017
VL - 27
IS - 1
SP - 207
EP - 222
AB - One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique. This paper focuses on using configurable properties of CLBs in the process of logic decomposition and technology mapping. A novel theory and a set of efficient techniques for logic decomposition based on a BDD are proposed. The paper shows that logic optimization can be efficiently carried out by using multiple decomposition. The essence of the proposed synthesis method is multiple cutting of a BDD. A new diagram form called an SMTBDD is proposed. Moreover, techniques that allow finding the best technology mapping oriented to configurability of CLBs are presented. In the experimental section, the presented method (MultiDec) is compared with academic and commercial tools. The experimental results show that the proposed technology mapping strategy leads to good results in terms of the number of CLBs.
LA - eng
KW - SMTBDD; FPGA; synthesis; decomposition
UR - http://eudml.org/doc/288101
ER -

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