# Stability of n -Bit Generalized Full Adder Circuits (GFAs). Part II

Formalized Mathematics (2008)

- Volume: 16, Issue: 1, page 73-80
- ISSN: 1426-2630

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topKatsumi Wasaki. " Stability of n -Bit Generalized Full Adder Circuits (GFAs). Part II ." Formalized Mathematics 16.1 (2008): 73-80. <http://eudml.org/doc/266606>.

@article{KatsumiWasaki2008,

abstract = {We continue to formalize the concept of the Generalized Full Addition and Subtraction circuits (GFAs), define the structures of calculation units for the Redundant Signed Digit (RSD) operations, then prove its stability of the calculations. Generally, one-bit binary full adder assumes positive weights to all of its three binary inputs and two outputs. We define the circuit structure of two-types n-bit GFAs using the recursive construction to use the RSD arithmetic logical units that we generalize full adder to have both positive and negative weights to inputs and outputs. The motivation for this research is to establish a technique based on formalized mathematics and its applications for calculation circuits with high reliability.MML identifier: GFACIRC2, version: 7.8.09 4.97.1001},

author = {Katsumi Wasaki},

journal = {Formalized Mathematics},

language = {eng},

number = {1},

pages = {73-80},

title = { Stability of n -Bit Generalized Full Adder Circuits (GFAs). Part II },

url = {http://eudml.org/doc/266606},

volume = {16},

year = {2008},

}

TY - JOUR

AU - Katsumi Wasaki

TI - Stability of n -Bit Generalized Full Adder Circuits (GFAs). Part II

JO - Formalized Mathematics

PY - 2008

VL - 16

IS - 1

SP - 73

EP - 80

AB - We continue to formalize the concept of the Generalized Full Addition and Subtraction circuits (GFAs), define the structures of calculation units for the Redundant Signed Digit (RSD) operations, then prove its stability of the calculations. Generally, one-bit binary full adder assumes positive weights to all of its three binary inputs and two outputs. We define the circuit structure of two-types n-bit GFAs using the recursive construction to use the RSD arithmetic logical units that we generalize full adder to have both positive and negative weights to inputs and outputs. The motivation for this research is to establish a technique based on formalized mathematics and its applications for calculation circuits with high reliability.MML identifier: GFACIRC2, version: 7.8.09 4.97.1001

LA - eng

UR - http://eudml.org/doc/266606

ER -

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