# Reduction in the number of PAL macrocells in the circuit of a Moore FSM

Alexander Barkalov; Larysa Titarenko; Sławomir Chmielewski

International Journal of Applied Mathematics and Computer Science (2007)

- Volume: 17, Issue: 4, page 565-575
- ISSN: 1641-876X

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topBarkalov, Alexander, Titarenko, Larysa, and Chmielewski, Sławomir. "Reduction in the number of PAL macrocells in the circuit of a Moore FSM." International Journal of Applied Mathematics and Computer Science 17.4 (2007): 565-575. <http://eudml.org/doc/207859>.

@article{Barkalov2007,

abstract = {Optimization methods of logic circuits for Moore finite-state machines are proposed. These methods are based on the existence of pseudoequivalent states of a Moore finite-state machine, a wide fan-in of PAL macrocells and free resources of embedded memory blocks. The methods are oriented to hypothetical VLSI microcircuits based on the CPLD technology and containing PAL macrocells and embedded memory blocks. The conditions of effective application of each proposed method are shown. An algorithm to choose the best model of a finite-state machine for given conditions is proposed. Examples of proposed methods application are given. The effectiveness of the proposed methods is also investigated.},

author = {Barkalov, Alexander, Titarenko, Larysa, Chmielewski, Sławomir},

journal = {International Journal of Applied Mathematics and Computer Science},

keywords = {complex programmable logic devices; Moore finite-state machine; pseudoequivalent states; logic circuit; design},

language = {eng},

number = {4},

pages = {565-575},

title = {Reduction in the number of PAL macrocells in the circuit of a Moore FSM},

url = {http://eudml.org/doc/207859},

volume = {17},

year = {2007},

}

TY - JOUR

AU - Barkalov, Alexander

AU - Titarenko, Larysa

AU - Chmielewski, Sławomir

TI - Reduction in the number of PAL macrocells in the circuit of a Moore FSM

JO - International Journal of Applied Mathematics and Computer Science

PY - 2007

VL - 17

IS - 4

SP - 565

EP - 575

AB - Optimization methods of logic circuits for Moore finite-state machines are proposed. These methods are based on the existence of pseudoequivalent states of a Moore finite-state machine, a wide fan-in of PAL macrocells and free resources of embedded memory blocks. The methods are oriented to hypothetical VLSI microcircuits based on the CPLD technology and containing PAL macrocells and embedded memory blocks. The conditions of effective application of each proposed method are shown. An algorithm to choose the best model of a finite-state machine for given conditions is proposed. Examples of proposed methods application are given. The effectiveness of the proposed methods is also investigated.

LA - eng

KW - complex programmable logic devices; Moore finite-state machine; pseudoequivalent states; logic circuit; design

UR - http://eudml.org/doc/207859

ER -

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